D/A conversion apparatus with offset compensation function and D/A conversion apparatus offset compensation method

ABSTRACT

An input changeover switch  40  is provided ahead of a comparator  50  that measures the DC offset of a D/A converter  30,  and a selective polarity inverter  60  is provided after comparator  50.  A first compensation value is generated by a compensation value generation section  12  and stored in a register  18.  Next, changeover switch  40  and polarity inverter  60  are switched and a second compensation value is generated, and is stored in a register  20.  Then an average compensation value is calculated by finding the arithmetic mean of the first and second compensation values by means of an average compensation value computation circuit  22,  and the input data is corrected with this average compensation value.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a D/A conversion apparatus with an offset compensation function and a D/A conversion apparatus offset compensation method.

[0003] 2. Description of the Related Art

[0004] In digital radio communication equipment, digitally modulated I (positive-phase) and Q (orthogonal) signals undergo D/A conversion, are combined in the radio frequency section of a radio telephone, and sent to an antenna as a radio signal. Ideally, the analog output voltage of a D/A converter would match an ideal output voltage corresponding to the digital input value (an analog output voltage that has no DC offset), but in reality, for various reasons DC offset occurs between the actual output and the ideal output.

[0005] In the case of a differential output D/A converter, when DC offset occurs between the D/A converter differential outputs corresponding to the I signal and Q signal (I+ and I−, or Q+ and Q−) (that is, when the D/A converter's differential output input/output characteristics are different), phase shift arises between the I and Q signals, resulting in transmission error.

[0006] It is therefore necessary to cancel DC offset between D/A converter differential outputs and adjust the D/A converter's characteristics.

[0007] In order to cancel DC offset between A/D converter differential outputs, it is first necessary to measure DC offset between D/A converter differential outputs for test data in a test mode—a state in which there are no input signals. A comparator (voltage comparison device) is used for this purpose.

[0008] Conventionally, +1 (high level) or −1 (low-level) obtained based on the result of voltage comparison by the comparator, is added to a compensation value (with an initial value of 0), and then the compensation value is subtracted from the test data to give the next D/A converter digital input. This procedure is then repeated until the polarity of the comparator changes. A technology whereby the compensation value at the time at which the polarity changes becomes the compensation value (control data) for compensating for DC offset between D/A converter differential outputs, and DC offset between D/A converter differential outputs is canceled by correcting the input data using this value, is described in patent documentation (Unexamined Japanese Patent Publication No.HEI 7-202693 (FIG. 1, FIG. 2, etc.)).

[0009] Actually, DC offset is also present in a comparator that detects D/A converter DC offset in a single output type D/A conversion apparatus, and in a comparator that detects DC offset between D/A converter differential outputs in a differential output type D/A conversion apparatus. Normally, comparator DC offset is designed to be kept within several mV.

[0010] However, investigation by the present inventors has confirmed that there are cases in which DC offset of a comparator itself is 20 mV or higher due to transistor size, variations in LSI structural process conditions, and so forth. In particular, there is a tendency for comparator DC offset to increase as transistor sizes become smaller.

[0011] The DC offset of a comparator constitutes error when D/A converter DC offset (including DC offset between differential outputs) is measured. Thus, if the DC offset of a comparator itself is large, accurate measurement is not possible, and D/A converter DC offset cannot be completely eliminated.

SUMMARY OF THE INVENTION

[0012] It is an object of the present invention to provide a D/A conversion apparatus with an offset compensation function and a D/A conversion apparatus offset compensation method that make it possible to almost completely eliminate D/A converter DC offset even when DC offset is present in a comparator.

[0013] According to an aspect of the invention, a D/A conversion apparatus with an offset compensation function detects D/A converter DC offset using a comparator, finds a compensation value based on the output signal of the comparator, corrects input data by performing addition or subtraction of the compensation value to/from the input data, and thereby compensates for the DC offset; and this D/A conversion apparatus with an offset compensation function has:

[0014] a changeover switch for selecting a first input mode in which a first and second signal respectively are input to a first and second input terminal of the comparator, and a second input mode in which the second and first signals respectively are input to the first and second input terminals of the comparator;

[0015] a polarity inversion section that inverts the polarity of the comparator output signal only when the second input mode is selected by means of this changeover switch; and

[0016] an input data correction section that in the first input mode finds a first compensation value based on the comparator output signal, in the second input mode finds a second compensation value based on a signal resulting from inversion of the comparator output signal by the polarity inversion section, then finds an average compensation value by calculating the average of the first and second compensation values, and also performs correction of the input data using the calculated average compensation value.

[0017] According to another aspect of the invention, a D/A conversion apparatus with an offset compensation function detects D/A converter DC offset using a comparator, finds a compensation value based on the output signal of the comparator, corrects input data by performing addition or subtraction of the compensation value to/from the input data, and thereby compensates for the DC offset; and this D/A conversion apparatus with an offset compensation function uses as the comparator a self-compensating comparator that has a function that cancels DC offset of this comparator itself;

[0018] wherein this self-compensating comparator has:

[0019] an operational amplifier;

[0020] a buffer or inverter;

[0021] a first switch for switching between connection and disconnection between the output terminal and inverse terminal of this operational amplifier;

[0022] a capacitor of which one side is connected to the inverse terminal of this operational amplifier; and

[0023] a second switch for switching between connection and disconnection between another output of this capacitor and a non-inverse terminal of the operational amplifier.

[0024] According to still another aspect of the invention, a D/A conversion apparatus offset compensation method detects D/A converter DC offset using a comparator, finds a compensation value based on the output signal of the comparator, corrects input data by performing addition or subtraction of the compensation value to/from the input data, and thereby compensates for the DC offset; and this D/A conversion apparatus offset compensation method has:

[0025] a step of inputting a first and second signal respectively to a first and second input terminal of the comparator, and finding a first compensation value based on the comparator output signal;

[0026] a step of inputting the second and first signal respectively to the first and second input terminal of the comparator, and finding a second compensation value based on a signal resulting from inversion of the comparator output signal by the polarity inversion section;

[0027] a step of finding an average compensation value by calculating the average of the first and second compensation values; and

[0028] a step of performing correction of the input data using this average compensation value.

BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and other objects and features of the invention will appear more fully hereinafter from a consideration of the following description taken in conjunction with the accompanying drawing wherein one example is illustrated by way of example, in which:

[0030]FIG. 1 is a drawing for explaining the configuration and operation (first compensation value generation operation) of a D/A conversion apparatus with an offset compensation function (in which the D/A converter has a differential output configuration) according to Embodiment 1 of the present invention;

[0031]FIG. 2 is a drawing for explaining the operation (second compensation value generation operation) of a D/A conversion apparatus with an offset compensation function, corresponding to Embodiment 1;

[0032]FIG. 3 is a drawing for explaining the operation (average compensation value generation operation) of a D/A conversion apparatus with an offset compensation function, corresponding to Embodiment 1;

[0033]FIG. 4 is a drawing for explaining the operation (operation whereby D/A conversion is performed while D/A converter DC offset is compensated for using an average compensation value) of a D/A conversion apparatus with an offset compensation function, corresponding to Embodiment 1;

[0034]FIG. 5A is a drawing showing the DC offset compensation value when there is no DC offset in the comparator in FIG. 4;

[0035]FIG. 5B is a drawing showing an example of differential output of the D/A converter in FIG. 5A;

[0036]FIG. 5C is a drawing showing the DC offset compensation value before input switching (at the time of non-crossing input) when there is DC offset in the comparator in FIG. 4;

[0037]FIG. 5D is a drawing showing an example of an addition value and subtraction value for canceling the comparator DC offset in FIG. 5D;

[0038]FIG. 5E is a drawing showing the DC offset compensation value after input switching (at the time of crossing input) when there is DC offset in the comparator in FIG. 4;

[0039]FIG. 5F is a drawing showing an example of an addition value and subtraction value for canceling the comparator DC offset in FIG. 5E;

[0040]FIG. 5G is a drawing showing that a DC offset compensation value based on an average compensation value is the same as a DC offset compensation value measured by a comparator with no DC offset (in the case of FIG. 5A) corresponding to Embodiment 1;

[0041]FIG. 6 is a drawing for explaining the reason why DC offset can be canceled in the D/A conversion apparatus with an offset compensation function in FIG. 4;

[0042]FIG. 7 is a drawing for explaining the configuration of a D/A conversion apparatus with an offset compensation function (in which the D/A converter has a single output configuration) according to Embodiment 2 of the present invention;

[0043]FIG. 8A is a drawing showing the DC offset compensation value when there is no DC offset in the comparator in FIG. 7;

[0044]FIG. 8B is a drawing showing the DC offset compensation value before input switching (at the time of non-crossing input) when there is DC offset in the comparator in FIG. 8A;

[0045]FIG. 8C is a drawing showing the DC offset compensation value after input switching (at the time of crossing input) when there is DC offset in the comparator in FIG. 8A;

[0046]FIG. 8D is a drawing showing that a DC offset compensation value based on an average compensation value is the same as a DC offset compensation value measured by a comparator with no DC offset (in the case of FIG. 8A)

[0047]FIG. 9 is a drawing showing the overall configuration of a D/A conversion apparatus with an offset compensation function in which an offset compensation function is provided for the comparator itself according to Embodiment 3 of the present invention;

[0048]FIG. 10 is a circuit diagram for explaining the actual configuration and operation (operation of generating a voltage corresponding to the comparator DC offset on both sides of a capacitor) of a D/A conversion apparatus with an offset compensation function, corresponding to Embodiment 3;

[0049]FIG. 11 is a circuit diagram for explaining the actual configuration and operation (operation of measuring D/A converter DC offset while canceling comparator DC offset) of a D/A conversion apparatus with an offset compensation function, corresponding to Embodiment 3;

[0050]FIG. 12A is a drawing showing DC offset arising in differential output of a D/A converter, corresponding to Embodiment 3;

[0051]FIG. 12B is a drawing showing the potential of different parts when an operational amplifier with no DC offset has a voltage following configuration, corresponding to Embodiment 3;

[0052]FIG. 12C is a drawing showing a mode in which a capacitor is connected to the inverse terminal of an operational amplifier with a voltage following configuration, corresponding to Embodiment 3;

[0053]FIG. 13A is a drawing showing an operational amplifier with DC offset, corresponding to Embodiment 3;

[0054]FIG. 13B is a drawing showing the state of the differential circuit in the operational amplifier with DC offset in FIG. 13A;

[0055]FIG. 13C is a drawing showing the potential of different parts of an operational amplifier and the state of the differential circuit in the operational amplifier when using a voltage following configuration, corresponding to Embodiment 3;

[0056]FIG. 13D is a drawing showing the potential of different parts when a capacitor is connected to the inverse terminal of the operational amplifier with a voltage following configuration in FIG. 13C;

[0057]FIG. 13E is a drawing showing the output voltage when the analog voltage input to the inverse terminal of an operational amplifier is corrected, and that corrected voltage is supplied to the operational amplifier, corresponding to Embodiment 3;

[0058]FIG. 13F is a drawing showing the output voltage when the output of the operational amplifier in FIG. 13E is inverted by an inverter;

[0059]FIG. 14A is a drawing showing the circuit configuration when there is no DC offset compensation function in a comparator for measuring DC offset between D/A converter differential outputs, corresponding to Embodiment 3;

[0060]FIG. 14B is a drawing showing the potential of outputs A+ and A− before compensation value measurement, and the potential of outputs A+ and A− after compensation value measurement, in the D/A converter in FIG. 14A;

[0061]FIG. 14C is a drawing showing the circuit configuration when there is a DC offset compensation function in a comparator for measuring DC offset between D/A converter differential outputs, corresponding to Embodiment 3;

[0062]FIG. 14D is a drawing showing the potential of outputs A+ and A− and the potential of the operational amplifier inputs before compensation value measurement, and the potential of the operational amplifier inputs after compensation value measurement, in the D/A converter in FIG. 14A;

[0063]FIG. 15 is a drawing showing the overall configuration of a D/A conversion apparatus with an offset compensation function in which an offset compensation function is provided for the comparator itself according to Embodiment 4 of the present invention;

[0064]FIG. 16A is a drawing showing the circuit configuration when there is no DC offset compensation function in a comparator for measuring D/A converter DC offset, corresponding to Embodiment 4;

[0065]FIG. 16B is a drawing showing the output potential before compensation value measurement and the output potential after compensation value measurement in the D/A converter in FIG. 16A;

[0066]FIG. 16C is a drawing showing the circuit configuration when there is a DC offset compensation function in a comparator for measuring D/A converter DC offset, corresponding to Embodiment 4; and

[0067]FIG. 16D is a drawing showing the output potential before compensation value measurement, the potential of the operational amplifier inputs, and the potential of the operational amplifier inputs after compensation value measurement, in the D/A converter in FIG. 16C;

[0068]FIG. 17 is a block diagram showing the configuration of a digital radio transmitter equipped with a D/A conversion apparatus with an offset compensation function (in an LSI implementation) according to Embodiment 5 of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0069] With reference now to the accompanying drawings, embodiments of the present invention will be explained in detail below.

Embodiment 1

[0070]FIG. 1 through FIG. 4 are block diagrams for explaining the configuration and operation of a D/A conversion apparatus with an offset compensation function according to Embodiment 1 of the present invention, and FIG. 5 and FIG. 6 are drawings for explaining the reason why DC offset of the comparator itself is canceled.

[0071] First, the configuration of a D/A conversion apparatus with an offset compensation function will be described using FIG. 1.

[0072] As shown in the figure, the D/A conversion apparatus has an input data correction section 10, a D/A converter 30 with a differential output configuration, a comparator 50, an input changeover switch 40 provided ahead of this comparator, and a polarity inverter 60 (comprising an inverter 62 and selector 64) for selectively inverting the polarity of the comparator 50 output signal. A low-pass filter may also be incorporated in D/A converter 30.

[0073] Input data correction section 10 has a compensation value generation section 12 (essentially composed of a counter 14 and register 26), two registers 18 and 20 for temporarily storing a first compensation value and second compensation value, an average compensation value computation circuit 22, a register 24 for storing the average compensation value computation result, and a subtracter 16 that subtracts a compensation value from the input data.

[0074] In this D/A conversion apparatus with an offset compensation function, the fact that comparator 50 itself has DC offset is taken into consideration, and total DC offset including the DC offset between the differential outputs of D/A converter 30 and the DC offset of comparator 50 itself is corrected by means of negative feedback control.

[0075] Next, the operation for compensating for DC offset will be described.

[0076] This operation is broadly divided into a stage in which a first compensation value is found in a test mode in which there is no signal to be sent on a radio path (FIG. 1), a stage in which a second compensation value is found (FIG. 2), and a stage in which an average compensation value is found (FIG. 3).

[0077] Then, as shown in FIG. 4, the DC offset between the differential outputs of D/A converter 30 can be eliminated by correcting normal input data using the found average compensation value.

[0078] A detailed description will now be given.

[0079] In FIG. 1, the operation (procedure) whereby a first compensation value is found in the test mode is indicated by bold lines.

[0080] First, test data (for example, digital input data corresponding to D/A converter 30 analog 0 V output (a value approximately intermediate between VDD and VSS)) is supplied to input data correction section 10.

[0081] Simultaneously with this, counter 14 starts operating. Counter 14 is incremented when the output of polarity inverter 60 connected to comparator 50 is +1 (high level), and is decremented when the output of polarity inverter 60 is −1 (low level). The count value is stored in register 26. It is here assumed that the count value of compensation value generation section 12 is used directly as a compensation value.

[0082] Initially, the count value of compensation value generation section 12 is zero, and therefore the supplied test data is output unchanged from subtracter 16, and is supplied to D/A converter 30 with a differential output configuration.

[0083] Complementary outputs with phases differing by 180° are obtained from D/A converter 30. These two output signals are designated “A+” and “A−”. A+ is a positive-phase output, and A− a negative-phase output, with respect to the digital input data. These signals are input to comparator 50 via changeover switch 40.

[0084] As shown in the figure, changeover switch 40 has a function of selectively connecting input terminals a and b to output terminals c and d.

[0085] In changeover switch 40 in FIG. 1, terminal a and terminal c are connected, and terminal b and terminal d are connected. In this state, a first input mode is selected.

[0086] In this first input mode, selector 64 in polarity inverter 60 passes the output signal from comparator 50 unchanged.

[0087] The comparator 50 output signal is supplied to counter 14 and register 26 functioning as compensation value generation section 12.

[0088] Counter 14 is incremented when this supplied comparator 50 output signal is +1 (high level) and decremented when the signal is −1 (low level). The count value is stored in register 26.

[0089] Subtracter 16 subtracts the register 26 value (count value) from the test data, and the resultant output is input to D/A converter 30 as the next digital input value.

[0090] Thereafter, the same operations are performed by looping, and these operations continue until the polarity of the comparator 50 output signal is inverted.

[0091] That is to say, on detecting inversion of the polarity of the comparator 50 output signal, compensation value generation section 12 saves the count value at that time (this being the first compensation value) in register 18.

[0092] Detection of polarity inversion must be carried out carefully, taking account of minute swings of the input voltage.

[0093] Next, as shown in FIG. 2, changeover switch 40 is controlled so that terminal a and terminal dare connected, and terminal band terminal care connected. In this state, a second input mode is selected.

[0094] At this time, selector 64 of polarity inverter 60 selects the output signal of inverter 62. That is to say, a signal with the polarity of comparator 50 output signal inverted is supplied to counter 14 and register 26.

[0095] In this state, the compensation value generation section 12 count value is restored to zero, and either the same operation as in FIG. 1 is performed, or an operation is performed to then find the second compensation value from the same count value as the first compensation value found in the operation in FIG. 1. The second compensation value obtained as a result is stored in register 20.

[0096] Then, as shown in FIG. 3, the first and second compensation values are fetched from register 18 and register 20, average compensation value computation circuit 22 calculates an average compensation value by performing an arithmetic mean operation, and this average compensation value is stored in register 24.

[0097] This average compensation value is the compensation value when comparator 50 has no offset whatever (that is to say, a compensation value whereby DC offset based on accurate measurement of DC offset between the differential outputs of D/A converter 30 can be completely canceled).

[0098] Therefore, DC offset between the differential outputs of D/A converter 30 can be completely eliminated by correcting normal input data using an obtained average compensation value, as shown in FIG. 4. The reason why the offset of comparator 50 itself is completely masked and made indiscernible by the above-described method will now be explained in detail using FIG. 5 and FIG. 6. It is here assumed that the minimum resolution (LSB) of the D/A converter is 1 mV.

[0099] In FIG. 5A, a case is assumed in which comparator 50 has no DC offset whatever.

[0100] When test data (test control value: data corresponding to 0 V) is supplied to D/A converter 30, since D/A converter differential outputs A+ and A− are mutually independent, if there happens to be DC offset in the D/A converter it appears as DC offset between the differential outputs. It is here assumed that, of the complementary outputs of D/A converter 30, the voltage of A+ is 20 mV and the voltage of A− is 0 mV.

[0101] Properly, the two outputs should both be 0 mV. In this case, therefore, 20 mV DC inter-differential-output DC offset has arisen.

[0102] Next, what kind of compensation value is necessary to cancel this 20 mV offset (how big a value should be used for the compensation value) will be considered.

[0103] The point to be noted here is that, in the case of a differential output type D/A converter, for a “+1” compensation value, −1 mV correction is performed for A+, and conversely, 1 mV correction is performed for A−.

[0104] That is to say, in the case of a differential output type D/A converter, for a “+1” compensation value, a total correction of −2 mV is applied between A+ and A−.

[0105] As stated above, there is now a 20 mV inter-differential-output DC offset between A+ and A−. Therefore, as shown in FIG. 5B, this offset can be canceled by performing correction so that 10 mV is subtracted from A+ (20 mV) and 10 mV is added to A− (0 V) (that is to say, by performing 10 mV correction when A+ and A− are considered individually).

[0106] Therefore, the necessary compensation value is “+10”.

[0107] Here, comparator 50 has DC offset, as shown in FIG. 5C (DC offset is here assumed to be such that the inverse terminal voltage is in effect 8 mV higher than the non-inverse terminal voltage).

[0108] In this case, the comparator 50 DC offset of 8 mV is added to the original D/A converter 30 inter-differential-output DC offset of 20 mV, and the DC offset is increased to 28 mV.

[0109] As shown in FIG. 5D, this 28 mV DC offset can be canceled by performing correction so that 14 mV is subtracted from A+ (20 mV) and 14 mV is added to A− (0 V).

[0110] Therefore, the necessary compensation value (first compensation value) is “+14”.

[0111] Next, the input to comparator 50 is switched as shown in FIG. 5E.

[0112] A+ (which has become +20 mV due to the effect of the D/A converter 30 DC offset) is thus input to the inverse terminal of comparator 50, and A− (0 mV) is input to the non-inverse terminal of comparator 50.

[0113] As a result, the comparator 50 DC offset of 8 mV is subtracted from the original D/A converter 30 inter-differential-output DC offset of 20 mV, giving 12 mV, and error is reduced. However, as −12 mV (=(−20 mV +8 mV) ) is applied as comparator 50 input, the polarity of comparator 50 output actually becomes negative. Thus, the polarity is inverted by inverter 62, and the compensation value is calculated.

[0114] As shown in FIG. 5F, this 12 mV DC offset can be canceled by performing correction so that 6 mV is subtracted from A+ (20 mV) and 6 mV is added to A− (0 V).

[0115] Thus, the compensation value (second compensation value) is “+6”.

[0116] Then, the arithmetic mean of the first compensation value and second compensation value is calculated, giving the average compensation value (=“+10”), as shown in FIG. 5G.

[0117] The value of this average compensation value matches the compensation value (=“+10”) obtained when comparator 50 has no DC offset at all, in FIG. 5A.

[0118] That is to say, the DC offset of comparator 50 itself is masked and made indiscernible, D/A converter 30 inter-differential-output DC offset is measured accurately, and based on this an accurate compensation value is obtained.

[0119] In other words, the D/A converter 30 inter-differential-output DC offset compensation value is“+10”, and whereas before comparator 50 input switching the DC offset compensation value of comparator 50 itself (=“+4”) is added to this original DC offset, after input switching the DC offset compensation value of comparator 50 itself (=“+4”) is subtracted.

[0120] That is to say, the polarity of the DC offset of comparator 50 itself is inverted after input switching as compared with before input switching.

[0121] On the other hand, the polarity of the original inter-differential-output DC offset (=+20 mV) of D/A converter 30 is the same before and after input switching. That is to say, after input switching, the output value polarity is reversed, but as this is inverted by inverter 62, the measured inter-differential-output DC offset compensation value remains at “+10”.

[0122] Therefore, when the first compensation value (compensation value 1) and second compensation value (compensation value 2) are added, the DC offset component of comparator 50 is canceled, and on the other hand the original inter-differential-output DC offset component of D/A converter 30 is doubled, so that by dividing this by 2, a compensation value corresponding to only the original inter-differential-output DC offset component of D/A converter 30 is obtained.

[0123] The principle of this DC offset cancellation is shown in easily understood form in FIG. 6.

[0124] If the original DC offset compensation value between differential outputs A+ and A− of D/A converter 30 is designated Voff, then Voff is “+10 (+20 mV equivalent) as explained above.

[0125] Before comparator 50 input switching (in the case of non-crossing input), comparator 50 offset DCoff (=+8 mV) is added. If the first compensation value (compensation value 1) is designated y, then y is “+14”.

[0126] On the other hand, after comparator 50 input switching (in the case of crossing input), comparator 50 offset DCoff (=+8 mV) is subtracted. If the second compensation value is designated x, then x is “+6”.

[0127] Here, x+y=2Voff.

[0128] Therefore, (x+y)/2=Voff=z, and this average compensation value z is the compensation value corresponding to the original inter-differential-output DC offset.

Embodiment 2

[0129]FIG. 7 shows an example in which the present invention is used for offset compensation for a single output type D/A converter 31.

[0130] One input (A+) of changeover switch 40 is the D/A converter 31 output signal, and the other input (A−) is a reference voltage (corresponding to the output voltage of an ideal D/A converter).

[0131] The remaining configuration is the same as that described above, and parts identical to those in the previously described example are assigned the same codes.

[0132] The characteristic operation of this embodiment is illustrated in FIGS. 8A through 8D. The operation is fundamentally the same as that described using FIG. 5. Here, too, assuming that the minimum resolution (LSB) of D/A converter 31 is 1 mV, in the case of single output type D/A converter 31, correction of −1 mV is applied only to A+ for a compensation value of “+1”. That is to say, the compensation value of a single output type D/A conversion apparatus is twice the compensation value of a differential output type D/A conversion apparatus.

[0133] That is to say, FIG. 8A shows the D/A converter 31 DC offset compensation value when there is no DC offset in comparator 50, FIG. 8B shows the D/A converter 31 DC offset compensation value (corresponding to the first compensation value) before input switching when there is DC offset in comparator 50, FIG. 8C shows the D/A converter 31 DC offset compensation value (corresponding to the second compensation value) after input switching when there is DC offset in comparator 50, and FIG. 8D shows that the average compensation value obtained by averaging the first and second compensation values matches the compensation value obtained in the case of FIG. 8A.

Embodiment 3

[0134]FIG. 9 is a block diagram showing an example of the configuration of a D/A conversion apparatus with an offset compensation function in which an operational amplifier 120 and inverter 140 are used instead of a comparator, and an offset compensation function is provided for operational amplifier 120 itself (that is to say, a self-compensating operational amplifier is used).

[0135] In this embodiment, D/A converter 30 inter-differential-output DC offset compensation is performed by means of input data compensation after DC offset of operational amplifier 120 is canceled by means of an analog technique using a capacitor C1.

[0136] In the previous embodiments, operational amplifier DC offset can be seen to be eliminated when viewing the overall system, but this embodiment differs in that operational amplifier 120 itself has an offset cancellation function, and is a self-compensating operational amplifier.

[0137] However, a point in common is that DC offset of the operational amplifier itself is canceled using information on DC offset of the operational amplifier.

[0138] First, the overall configuration of the D/A conversion apparatus in FIG. 9 will be described.

[0139] As shown in the figure, input data correction section 100 has a compensation value generation section 110 (comprising a counter 102 and register 104), and a subtracter 106.

[0140] As in the previous embodiments, the counter 102 count value is used directly as a compensation value via register 104.

[0141] Register 104 also has a function of storing the counter value when the polarity of the operational amplifier 120 output signal is inverted.

[0142] In this embodiment, a complementary output type (differential output type) D/A converter 30 is used.

[0143] Also provided are a first switch (SW1) that switches between connection and disconnection between the output terminal and inverse input terminal of operational amplifier 120 that has an offset cancellation function, and a capacitor C1 one side of which is connected to the inverse input terminal of operational amplifier 120, and the other side of which is connected to a second switch (SW2).

[0144] The second switch is provided on the other side of capacitor C1 in order to switch between supplying the output A− voltage to the b terminal side constituting one side of D/A converter 30 and supplying the output A+ voltage to the a terminal side constituting the other side.

[0145] The non-inverse input terminal of operational amplifier 120 is connected to above-mentioned terminal a, and the operational amplifier 120 output terminal is connected to the input terminal of inverter 140. The inverter 140 output terminal is connected to counter 102 and register 104.

[0146] In this embodiment, first, the second switch (SW2) is switched to the terminal a side, the first switch (SW1) is turned on, and operational amplifier 120 is given a voltage following configuration, whereby a voltage corresponding to the operational amplifier 120 DC offset is generated on both sides of capacitor C1.

[0147] Next, the first switch (SW1) is turned off, and the operational amplifier 120 is restored to a comparator configuration. Then the second switch (SW2) is switched to the terminal b side. Then, when in the test mode, an inter-differential-output DC offset occurs between A+ and A−. Therefore, a voltage resulting from adding a voltage corresponding to the operational amplifier 120 DC offset to the inter-differential-output DC offset of D/A converter 30 is input between the operational amplifier 120 input terminals.

[0148] By this means, the voltage input to the inverse terminal of operational amplifier 120 is corrected by the amount of operational amplifier 120 DC offset.

[0149] Therefore, the operational amplifier 120 DC offset is canceled. Thus, the DC offset between the D/A converter 30 differential outputs can be measured accurately.

[0150] The procedure will now be described in detail. First, in the circuit in FIG. 9, when test data is input an analog voltage corresponding to the test data is generated in D/A converter 30 outputs A+ and A−.

[0151]FIG. 10 is a drawing for explaining in detail the operation whereby a voltage corresponding to the operational amplifier 120 DC offset is generated on both sides of capacitor C1.

[0152] As shown in the figure, operational amplifier 120 is composed of NMOS transistors (M3 and M4), current mirror loads (M1 and M2), and a constant current source I3.

[0153] In FIG. 10, first switch SW1 is turned on, giving a voltage following configuration. Second switch SW2 is switched to the terminal a side.

[0154] The voltage of A−, one of the outputs of D/A converter 30, is supplied to the gate of NMOS transistor M3 and terminal a on the switch SW2 side of capacitor C1.

[0155] As operational amplifier 120 has a voltage following configuration, the voltages of the inverse terminal (gate of NMOS transistor M4), non-inverse terminal (gate of NMOS transistor M3), and output terminal (point of connection of the drain of PMOS transistor M2 comprising a current mirror load and the drain of NMOS transistor M4) should all logically go to the “A− potential” and match.

[0156] In fact, however, there is DC offset in operational amplifier 120, and the gate potentials of the NMOS transistors (M3 and M4) comprising a differential pair do not match.

[0157] In FIG. 10, the drive capability of NMOS transistor M3 is assumed to be greater than the drive capability of NMOS transistor M4. That is to say, the channel conductance (W/L) of NMOS transistor M3 is assumed to be greater than the channel conductance of NMOS transistor M4.

[0158] Fundamentally, a current obtained by equal division of the constant current source I3 current flows in the left and right circuits of the differential pair, but if there is a difference in the current capacity of NMOS transistors M3 and M4, the current that flows through NMOS transistor M3 (I1) is greater than the current that flows through NMOS transistor M4 (I2), and the balance of the current amount of the left and right circuits is lost.

[0159] At this time, operational amplifier 120 operates to reduce this imbalance between currents I1 and I2 by means of negative feedback control.

[0160] That is to say, in the current mirror loads (M1 and M2), an output current (=I1) equal to the input current (=I1) is sent from NMOS transistor M2. On the other hand, differential pair transistor M4 takes in only a current corresponding to current I2.

[0161] Therefore, the difference between current I1 and current I2, I4 (=I1-I2), leaks outside the differential circuitry via a negative feedback loop (including switch SW1 in the off state), and capacitor C1 is charged. As a result, the gate voltage of NMOS transistor M4 rises.

[0162] That is to say, the gate potential of NMOS transistor M4 rises so that a larger current flows in NMOS transistor M4, which has low current capacity, and when the currents flowing through differential pair NMOS transistors M3 and M4 become equal (that is, when I1=I2 and the current amounts in the left and right circuits are balanced), the rise of the gate potential of NMOS transistor M4 stops.

[0163] As a result, the gate potential of NMOS transistor M4 becomes higher than the gate potential of NMOS transistor M3, and a potential difference (corresponding to the operational amplifier 120 DC offset (DCoff)) occurs on either side of capacitor C1.

[0164] Next, as shown in FIG. 11, first switch SW1 is turned off, the operational amplifier 120 negative feedback loop is terminated, and second switch SW2 is switched to the terminal b side.

[0165] When this is done, the A+ voltage is applied to the second switch SW2 side of capacitor C1 (to which A− was being applied until immediately prior thereto).

[0166] At this time, a voltage resulting from adding DC offset DCoff of operational amplifier 120 itself to A+ (A+)+DCoff) is applied to the gate of NMOS transistor M4 (the inverse terminal of operational amplifier 120). That is to say, a corrected input analog voltage is input to the inverse terminal of operational amplifier 120.

[0167] As stated above, the current capacity of NMOS transistor M4 is lower than that of NMOS transistor M3. Thus, the voltage that should be applied to the inverse terminal in order to eliminate the resultant imbalance in left and right currents is a voltage corresponding to DCoff.

[0168] Therefore, by adding a voltage corresponding to DCoff to the input voltage (A+) beforehand, the imbalance of differential circuit left and right currents in operational amplifier 120 is automatically eliminated.

[0169] That is to say, the DC offset of operational amplifier 120 itself is masked and made indiscernible, and is canceled.

[0170] In this state, operation of counter 102 is started, and a compensation value acquisition operation is started in order to compensate for DC offset in the differential outputs of D/A converter 30.

[0171] As the DC offset of operational amplifier (comparator) 120 itself has been canceled, the DC offset of the differential outputs of D/A converter 30 is measured accurately, and a compensation value is calculated based on the measured DC offset value.

[0172] Therefore, the influence of the DC offset of operational amplifier 120 itself is eliminated, and a highly precise compensation value can be generated.

[0173] The above operations will now be summarized while referring to FIG. 12 and FIG. 13.

[0174] The problem considered here is how to measure accurately the DC offset between D/A converter 30 differential outputs (A− and A+), as shown in FIG. 12A.

[0175] Properly, the differential outputs (A− and A+) should both be 0 V, but here, A+ is 20 mV (while A− is 0 mV), and there is a 20 mV inter-differential-output DC offset.

[0176] Before the D/A converter 30 offset is measured, it is necessary to cancel the offset of operational amplifier (comparator) 120 itself.

[0177] First, it is assumed that there is no DC offset in operational amplifier (comparator) 120 itself.

[0178] Here, as shown in FIG. 12B, when an operational amplifier with no DC offset is given a voltage following configuration, and A− (=0 mV) is input to the non-inverse terminal, inverse terminal also becomes A− due to virtual grounding, and thus the output of operational amplifier 120 also becomes A−.

[0179] Here, as shown in FIG. 12C, if one side of capacitor C1 is connected to the inverse terminal of operational amplifier 120, and the other side is connected to the non-inverse terminal, the potential on either side of capacitor C1 is A−, and there is no potential difference.

[0180] Next, a case is considered in which DC offset is present in operational amplifier 120 itself, as shown in FIG. 13A.

[0181] The expression “DC offset is present in operational amplifier 120 itself” means that when the inverse terminal and non-inverse terminal are made the same potential (=A−) as shown in FIG. 13B, the current amounts of currents I1 and I2 of the left and right differential circuitry are different. Here, I1>I2.

[0182] Next, operational amplifier 120 is given a voltage following configuration, as shown in FIG. 13C.

[0183] When this is done, the voltage of the inverse terminal of compensation value generation section 12 rises so as to eliminate the imbalance between currents I1 and I2, as shown in the drawing enclosed by a dotted line in the lower part of FIG. 13C. In the figure, this raised voltage is denoted by reference character “α”. This voltage α corresponds to the DC offset DCoff of operational amplifier 120 itself.

[0184] Here, when a configuration such as shown in FIG. 13D is set, a potential difference of voltage α occurs on either side of capacitor C1. Here, α=Q/C (Q: charge, C: capacitance of capacitor C1).

[0185] Next, as shown in FIG. 13E, the input voltage to the inverse terminal of operational amplifier 120 is switched from A− (=0 mV) to A+ (=20 mV). In this case, still, the potential difference of voltage α is kept in capacitor C1.

[0186] Then α is added to original input A+ at the inverse terminal of operational amplifier 120, and the analog voltage input to the inverse terminal is corrected.

[0187] Thus voltage α is necessary to eliminate the imbalance of differential circuit left and right currents in operational amplifier 120, as shown in FIG. 13C (that is to say, voltage α is a voltage equivalent to DCoff). Therefore, the DC offset of operational amplifier 120 is automatically canceled by adding this voltage α to the input analog voltage beforehand.

[0188] However, in FIG. 13E, A+ (20 mV) is input to the inverse terminal of operational amplifier 120, and therefore the polarity of the operational amplifier 120 output is inverted.

[0189] Thus, the polarity is inverted by inverter 140, as shown in FIG. 13F. By this means, D/A converter 30 inter-differential-output DC offset “+20 mV” (see FIG. 12A) is determined accurately.

[0190] Thus a compensation value is calculated by accurately determining the DC offset between D/A 30 converter differential outputs. Consequently, it is possible to accurately compensate for DC offset between D/A 30 converter differential outputs.

[0191] Thus, according to this embodiment, a capacitor is connected to the inverse terminal of the operational amplifier, and the input voltage is stepped up (or stepped down) by using this capacitor as a bootstrap capacitor.

[0192] The point to be noted here is that, in this embodiment, the voltage is not simply stepped up (stepped down), but the amount of change of the voltage is made to match the DC offset of the operational amplifier itself, whereby the analog voltage input to the inverse input terminal of the operational amplifier is corrected beforehand so that the DC offset of the operational amplifier can be canceled.

[0193] That is to say, in this embodiment, a capacitor functions as a means of correcting the inverse terminal input voltage. Then, such operation is implemented solely by means of simple control comprising appropriate switching of switches, as described using FIG. 9 through FIG. 13.

[0194] Also, the configuration of this embodiment can be implemented by adding a capacitor and switches to the operational amplifier. The configuration is thus extremely simple, and implementation is easy.

[0195] The above-described features of this embodiment are summarized in FIGS. 14A through 14D.

[0196] First, an explanation will be given concerning a compensation value (a compensation value for compensating for D/A converter DC offset) in a case where operational amplifier 120 DC offset compensation is not performed, using FIGS. 14A and 14B.

[0197] Here, FIG. 14A shows the connection of D/A converter 30, operational amplifier 120, and inverter 140 in the case of an operational amplifier for which there is no DC offset compensation, and FIG. 14B shows the potentials of D/A converter outputs A+ and A− before compensation value measurement and the potentials of A+ and A− after compensation value measurement.

[0198] In this case, “DC offset compensation value×2LSB (where LSB is equivalent to 1 mV)” is “D/A converter DC offset−operational amplifier DC offset (DCoff)”, and there is an amount of error equivalent to DCoff.

[0199] Next, an explanation will be given concerning a compensation value (a compensation value for compensating for D/A converter DC offset) in a case where operational amplifier 120 DC offset compensation is performed, using FIGS. 14C and 14D.

[0200] Here, FIG. 14C shows the connection of D/A converter 30, capacitor C1, operational amplifier 120, and inverter 140 in the case of an operational amplifier for which there is DC offset compensation, and FIG. 14D shows the potentials of D/A converter outputs A+ and A− and the potentials of the operational amplifier inputs before compensation value measurement, and the potentials of the operational amplifier inputs after compensation value measurement.

[0201] In this case, “DC offset compensation value×2LSB” is “D/A converter DC offset+operational amplifier DC offset (DCoff)−DCoff”, and operational amplifier 120 DC offset is canceled, leaving the DC offset of D/A converter 30 itself, thereby enabling the DC offset of D/A converter 30 to be measured accurately.

Embodiment 4

[0202]FIG. 15 shows a configuration whereby output voltage Vout of a single output type D/A converter 31 is compared with a reference voltage (corresponding to the output voltage of an ideal D/A converter).

[0203] The basic configuration is the same as that of the previous embodiments, but the configuration differs in that the non-inverse terminal of operational amplifier 120 is connected to a reference voltage (Vref). It is here assumed that D/A converter 31 output voltage Vout is a positive-phase output with respect to digital input data.

[0204] The operation is fundamentally similar to that of Embodiment 3. However, a difference is that, as explained earlier, the compensation value for a single output type D/A conversion apparatus is twice the compensation value for a differential output type D/A conversion apparatus.

[0205] Using FIG. 16, explanations will be given concerning the DC offset compensation value in the case of an operational amplifier for which there is no DC offset compensation, and in the case of an operational amplifier for which there is DC offset compensation.

[0206]FIG. 16A shows the connection of D/A converter 31, operational amplifier 120, and inverter 140 in the case of an operational amplifier for which there is no DC offset compensation, and FIG. 16B shows the potential of D/A converter 31 output Vout and the potential of Vref before compensation value measurement, and the potentials of Vout and Vref after compensation value measurement.

[0207] At this time, “DC offset compensation value×LSB” is the DC offset (DCoff) of operational amplifier 120 of D/A converter 31, and there is an amount of error equivalent to DCoff.

[0208]FIG. 16C shows the connection of D/A converter 31, capacitor C1, operational amplifier 120, and inverter 140 in the case of an operational amplifier for which there is DC offset compensation, and FIG. 16D shows the potential of D/A converter 31 output Vout, the potential of Vref, the operational amplifier input potential before compensation value measurement, and the operational amplifier input potential after compensation value measurement.

[0209] Therefore, as shown in FIG. 16D, “DC offset compensation value×LSB” can be expressed as “D/A converter DC offset+operational amplifier DC offset (DCoff)−DCoff”. Operational amplifier 120 DC offset is canceled, leaving the DC offset of D/A converter 31 itself, thereby enabling the DC offset of D/A converter 31 to be measured accurately.

Embodiment 5

[0210]FIG. 17 is a block diagram showing the configuration of a digital radio transmitter that uses a D/A conversion apparatus with an offset compensation function of the present invention.

[0211] As shown in the figure, the digital radio transmitter has a digital modulator 300, D/A conversion apparatuses (which are D/A conversion apparatuses with an offset compensation function of the present invention) 500 a and 500 b corresponding to I and Q respectively, an orthogonal modulator 600, a transmission circuit 700, and an antenna 710. Digital modulator 300 is a QPSK modulator, for example.

[0212] Digital modulator 300, D/A conversion apparatuses 500 a and 500 b, orthogonal modulator 600, and transmission circuit 700 are integrated in a single LSI.

[0213] As DC offset has been canceled, the input/output characteristics of the two D/A conversion apparatuses 500 a and 500 b match, and the phases of the I and Q transmit signals match, making possible accurate transmission.

[0214] A D/A conversion apparatus with an offset compensation function of the present invention can be used not only for communication, but also in audio equipment, etc.

[0215] According to the above-described invention, it is possible to almost completely eliminate D/A converter DC offset even when DC offset is present in a comparator. Also, the configuration of this invention is simple and the control method is also simple, and therefore implementation is easy. Moreover, as analog circuitry becomes finer, comparator DC offset will increase. Thus, the present invention is extremely effective as a means of implementing a D/A converter from which DC offset is almost completely eliminated, using a fine process.

[0216] The present invention is not limited to the above-described embodiments, and various variations and modifications may be possible without departing from the scope of the present invention.

[0217] This application is based on Japanese Patent Application No. 2003-004041 filed on Jan. 10, 2003, entire content of which is expressly incorporated by reference herein. 

What is claimed is:
 1. A D/A conversion apparatus with an offset compensation function that detects D/A converter DC offset using a comparator, finds a compensation value based on an output signal of said comparator, corrects input data by performing addition or subtraction of said compensation value to/from input data, and thereby compensates for said DC offset; said D/A conversion apparatus with an offset compensation function comprising: a changeover switch for selecting a first input mode in which a first and second signal respectively are input to a first and second input terminal of said comparator, and a second input mode in which said second and first signals respectively are input to said first and second input terminals of said comparator; a polarity inversion section that inverts polarity of an output signal of said comparator only when said second input mode is selected by means of this changeover switch; and an input data correction section that in said first input mode finds a first compensation value based on an output signal of said comparator, in said second input mode finds a second compensation value based on a signal resulting from inversion of an output signal of said comparator by said polarity inversion section, then finds an average compensation value by calculating an average of said first and second compensation values, and also performs correction of said input data using calculated said average compensation value.
 2. The D/A conversion apparatus with an offset compensation function according to claim 1, wherein: said D/A converter is a differential output type that outputs two analog signals whose phases differ by 180°; and these two analog signals are said first and second signals respectively in said changeover switch.
 3. The D/A conversion apparatus with an offset compensation function according to claim 1, wherein an output signal of a single output type D/A converter and a predetermined reference voltage are said first and second signals respectively in said changeover switch.
 4. The D/A conversion apparatus with an offset compensation function according to claim 1, wherein DC offset is present in said comparator itself, said D/A converter DC offset and DC offset of said comparator itself are both compensated for by correction of said input data, and thereby said comparator functions as a comparator in which there is essentially no DC offset.
 5. A D/A conversion apparatus with an offset compensation function that detects D/A converter DC offset using a comparator, finds a compensation value based on an output signal of said comparator, corrects input data by performing addition or subtraction of said compensation value to/from input data, and thereby compensates for said DC offset; and that uses as said comparator a self-compensating comparator that has a function that cancels DC offset of this comparator itself; wherein said self-compensating comparator comprises: an operational amplifier; a buffer or inverter; a first switch for switching between connection and disconnection between an output terminal and inverse terminal of this operational amplifier; a capacitor of which one side is connected to said inverse terminal of said operational amplifier; and a second switch for switching between connection and disconnection between another output of this capacitor and a non-inverse terminal of said operational amplifier.
 6. The D/A conversion apparatus with an offset compensation function according to claim 5, wherein before a compensation value for canceling said D/A converter DC offset is found, an offset cancellation operation is executed for said self-compensating comparator; and also when this offset cancellation operation for said self-compensating comparator is executed: first, said first switch is turned on, and said output terminal and said input terminal of said operational amplifier are shorted and voltage following by means of 100% negative feedback is configured, and also another terminal of said capacitor and said non-inverse terminal of said operational amplifier are connected by said second switch and that connection point is made a predetermined potential, whereby a voltage corresponding to a DC offset of said operational amplifier is generated on both sides of said capacitor; then said first switch is turned off and said output terminal and said inverse terminal of said operational amplifier are disconnected, and also said other terminal of said capacitor is disconnected from said non-inverse terminal of said operational amplifier by means of said second switch; and then a signal necessary for measuring DC offset of said D/A converter is supplied to said other terminal of said capacitor and said non-inverse terminal of said operational amplifier, and at this time DC offset of said operational amplifier is canceled with a voltage corresponding to DC offset of said operational amplifier generated by said capacitor.
 7. An LSI incorporating the D/A conversion apparatus with an offset compensation function according to claim
 1. 8. A D/A conversion apparatus offset compensation method that detects D/A converter DC offset using a comparator, finds a compensation value based on an output signal of said comparator, corrects input data by performing addition or subtraction of said compensation value to/from input data, and thereby compensates for said DC offset; said D/A conversion apparatus offset compensation method comprising: a step of inputting a first and second signal respectively to a first and second input terminal of said comparator, and finding a first compensation value based on an output signal of said comparator; a step of inputting said second and first signal respectively to said first and second input terminal of said comparator, and finding a second compensation value based on a signal resulting from inversion of an output signal of said comparator by said polarity inversion section; a step of finding an average compensation value by calculating an average of said first and second compensation values; and a step of performing correction of input data using this average compensation value.
 9. A D/A conversion apparatus offset compensation method whereby offset cancellation is performed via the operation according to claim 6 for said self-compensating comparator constituent to the D/A conversion apparatus according to claim 5, then said compensation value is found using that self-compensating comparator for which DC offset has been canceled, input data correction is performed using this compensation value, and thereby said D/A converter DC offset is compensated for. 